////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: L.33
//  \   \         Application: netgen
//  /   /         Filename: clock_generator_map.v
// /___/   /\     Timestamp: Fri Apr 02 20:57:11 2010
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -s 5 -pcf clock_generator.pcf -sdf_anno true -sdf_path netgen/map -insert_glbl true -w -dir netgen/map -ofmt verilog -sim clock_generator_map.ncd clock_generator_map.v 
// Device	: 3s500efg320-5 (PRODUCTION 1.27 2009-03-03)
// Input file	: clock_generator_map.ncd
// Output file	: F:\Tesis\FPGA\netgen\map\clock_generator_map.v
// # of Modules	: 1
// Design Name	: clock_generator
// Xilinx        : C:\Xilinx\11.1\ISE
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module clock_generator (
  clock8, reset, clock_in, clock50, clk16, clock_PS1, clock_PS2, clock_PS3
);
  output clock8;
  input reset;
  input clock_in;
  output clock50;
  output clk16;
  output clock_PS1;
  output clock_PS2;
  output clock_PS3;
  wire clock50_OBUF_71;
  wire clock_PS1_OBUF_72;
  wire clock_PS2_OBUF_73;
  wire clock_PS3_OBUF_74;
  wire reset_IBUF_75;
  wire clock8_OBUF_76;
  wire clk16_OBUF_77;
  wire PS1;
  wire GLOBAL_LOGIC1;
  wire PS2;
  wire GLOBAL_LOGIC0;
  wire clock_locked;
  wire \clock16_generator/CLKFX_BUF ;
  wire PS3;
  wire CLK8;
  wire \clock50/O ;
  wire \clock_in/INBUF ;
  wire \clock_PS1/O ;
  wire \clock_PS2/O ;
  wire \clock_PS3/O ;
  wire \reset/INBUF ;
  wire \clock8/O ;
  wire \clk16/O ;
  wire \PS1_BUFG_INST/S_INVNOT ;
  wire \PS2_BUFG_INST/S_INVNOT ;
  wire \clock16_generator/DCM_SP_INST/CLK0 ;
  wire \clock16_generator/DCM_SP_INST/CLK90 ;
  wire \clock16_generator/DCM_SP_INST/CLK180 ;
  wire \clock16_generator/DCM_SP_INST/CLK270 ;
  wire \clock16_generator/DCM_SP_INST/CLK2X ;
  wire \clock16_generator/DCM_SP_INST/CLK2X180 ;
  wire \clock16_generator/DCM_SP_INST/CLKDV ;
  wire \clock16_generator/DCM_SP_INST/CLKFX180 ;
  wire \clock16_generator/DCM_SP_INST/STATUS7 ;
  wire \clock16_generator/DCM_SP_INST/STATUS6 ;
  wire \clock16_generator/DCM_SP_INST/STATUS5 ;
  wire \clock16_generator/DCM_SP_INST/STATUS4 ;
  wire \clock16_generator/DCM_SP_INST/STATUS3 ;
  wire \clock16_generator/DCM_SP_INST/STATUS2 ;
  wire \clock16_generator/DCM_SP_INST/STATUS1 ;
  wire \clock16_generator/DCM_SP_INST/STATUS0 ;
  wire \clock16_generator/DCM_SP_INST/PSDONE ;
  wire \clock16_generator/DCM_SP_INST/CLKFB_BUF_165 ;
  wire \clock16_generator/DCM_SP_INST/CLKIN_BUF_164 ;
  wire \PS3_BUFG_INST/S_INVNOT ;
  wire \clock16_generator/CLKFX_BUFG_INST/S_INVNOT ;
  wire \CLK8_BUFG_INST/S_INVNOT ;
  wire \PS2/DXMUX_228 ;
  wire \PS2/DYMUX_219 ;
  wire PS1_input;
  wire \PS2/SRINV_209 ;
  wire \PS2/CLKINV_208 ;
  wire \PS2/CEINV_207 ;
  wire \PS3/DYMUX_245 ;
  wire \PS3/CLKINV_242 ;
  wire \PS3/CEINV_241 ;
  wire \CLK8/DYMUX_262 ;
  wire \CLK8/CLKINV_259 ;
  wire \CLK8/CEINV_258 ;
  wire \CLK8/FFY/RSTAND_268 ;
  wire \PS3/FFY/RSTAND_251 ;
  wire GND;
  wire \NLW_clock16_generator/DCM_SP_INST_DSSEN_UNCONNECTED ;
  wire VCC;
  initial $sdf_annotate("netgen/map/clock_generator_map.sdf");
  X_OPAD   \clock50/PAD  (
    .PAD(clock50)
  );
  X_OBUF   clock50_OBUF (
    .I(\clock50/O ),
    .O(clock50)
  );
  X_IPAD   \clock_in/PAD  (
    .PAD(clock_in)
  );
  X_BUF   \clock16_generator/CLKIN_IBUFG_INST  (
    .I(clock_in),
    .O(\clock_in/INBUF )
  );
  X_BUF   \clock_in/IFF/IMUX  (
    .I(\clock_in/INBUF ),
    .O(clock50_OBUF_71)
  );
  X_OPAD   \clock_PS1/PAD  (
    .PAD(clock_PS1)
  );
  X_OBUF   clock_PS1_OBUF (
    .I(\clock_PS1/O ),
    .O(clock_PS1)
  );
  X_OPAD   \clock_PS2/PAD  (
    .PAD(clock_PS2)
  );
  X_OBUF   clock_PS2_OBUF (
    .I(\clock_PS2/O ),
    .O(clock_PS2)
  );
  X_OPAD   \clock_PS3/PAD  (
    .PAD(clock_PS3)
  );
  X_OBUF   clock_PS3_OBUF (
    .I(\clock_PS3/O ),
    .O(clock_PS3)
  );
  X_IPAD   \reset/PAD  (
    .PAD(reset)
  );
  X_BUF   reset_IBUF (
    .I(reset),
    .O(\reset/INBUF )
  );
  X_BUF   \reset/IFF/IMUX  (
    .I(\reset/INBUF ),
    .O(reset_IBUF_75)
  );
  X_OPAD   \clock8/PAD  (
    .PAD(clock8)
  );
  X_OBUF   clock8_OBUF (
    .I(\clock8/O ),
    .O(clock8)
  );
  X_OPAD   \clk16/PAD  (
    .PAD(clk16)
  );
  X_OBUF   clk16_OBUF (
    .I(\clk16/O ),
    .O(clk16)
  );
  X_BUFGMUX   PS1_BUFG_INST (
    .I0(PS1),
    .I1(GND),
    .S(\PS1_BUFG_INST/S_INVNOT ),
    .O(clock_PS1_OBUF_72)
  );
  X_INV   \PS1_BUFG_INST/SINV  (
    .I(GLOBAL_LOGIC1),
    .O(\PS1_BUFG_INST/S_INVNOT )
  );
  X_BUFGMUX   PS2_BUFG_INST (
    .I0(PS2),
    .I1(GND),
    .S(\PS2_BUFG_INST/S_INVNOT ),
    .O(clock_PS2_OBUF_73)
  );
  X_INV   \PS2_BUFG_INST/SINV  (
    .I(GLOBAL_LOGIC1),
    .O(\PS2_BUFG_INST/S_INVNOT )
  );
  X_DCM_SP #(
    .DUTY_CYCLE_CORRECTION ( "TRUE" ),
    .CLKDV_DIVIDE ( 2.000000 ),
    .CLKFX_DIVIDE ( 25 ),
    .CLKFX_MULTIPLY ( 8 ),
    .CLKOUT_PHASE_SHIFT ( "NONE" ),
    .CLKIN_PERIOD ( 20.0000000000000000 ),
    .DFS_FREQUENCY_MODE ( "LOW" ),
    .STARTUP_WAIT ( "FALSE" ),
    .CLK_FEEDBACK ( "NONE" ),
    .DLL_FREQUENCY_MODE ( "LOW" ),
    .CLKIN_DIVIDE_BY_2 ( "FALSE" ),
    .PHASE_SHIFT ( 0 ))
  \clock16_generator/DCM_SP_INST  (
    .CLKIN(\clock16_generator/DCM_SP_INST/CLKIN_BUF_164 ),
    .CLKFB(\clock16_generator/DCM_SP_INST/CLKFB_BUF_165 ),
    .RST(reset_IBUF_75),
    .DSSEN(\NLW_clock16_generator/DCM_SP_INST_DSSEN_UNCONNECTED ),
    .PSINCDEC(GLOBAL_LOGIC0),
    .PSEN(GLOBAL_LOGIC0),
    .PSCLK(GLOBAL_LOGIC0),
    .PSDONE(\clock16_generator/DCM_SP_INST/PSDONE ),
    .LOCKED(clock_locked),
    .CLKFX180(\clock16_generator/DCM_SP_INST/CLKFX180 ),
    .CLKFX(\clock16_generator/CLKFX_BUF ),
    .CLKDV(\clock16_generator/DCM_SP_INST/CLKDV ),
    .CLK2X180(\clock16_generator/DCM_SP_INST/CLK2X180 ),
    .CLK2X(\clock16_generator/DCM_SP_INST/CLK2X ),
    .CLK270(\clock16_generator/DCM_SP_INST/CLK270 ),
    .CLK180(\clock16_generator/DCM_SP_INST/CLK180 ),
    .CLK90(\clock16_generator/DCM_SP_INST/CLK90 ),
    .CLK0(\clock16_generator/DCM_SP_INST/CLK0 ),
    .STATUS({\clock16_generator/DCM_SP_INST/STATUS7 , \clock16_generator/DCM_SP_INST/STATUS6 , \clock16_generator/DCM_SP_INST/STATUS5 , 
\clock16_generator/DCM_SP_INST/STATUS4 , \clock16_generator/DCM_SP_INST/STATUS3 , \clock16_generator/DCM_SP_INST/STATUS2 , 
\clock16_generator/DCM_SP_INST/STATUS1 , \clock16_generator/DCM_SP_INST/STATUS0 })
  );
  X_BUF   \clock16_generator/DCM_SP_INST/CLKFB_BUF  (
    .I(GLOBAL_LOGIC0),
    .O(\clock16_generator/DCM_SP_INST/CLKFB_BUF_165 )
  );
  X_BUF   \clock16_generator/DCM_SP_INST/CLKIN_BUF  (
    .I(clock50_OBUF_71),
    .O(\clock16_generator/DCM_SP_INST/CLKIN_BUF_164 )
  );
  X_BUFGMUX   PS3_BUFG_INST (
    .I0(PS3),
    .I1(GND),
    .S(\PS3_BUFG_INST/S_INVNOT ),
    .O(clock_PS3_OBUF_74)
  );
  X_INV   \PS3_BUFG_INST/SINV  (
    .I(GLOBAL_LOGIC1),
    .O(\PS3_BUFG_INST/S_INVNOT )
  );
  X_BUFGMUX   \clock16_generator/CLKFX_BUFG_INST  (
    .I0(\clock16_generator/CLKFX_BUF ),
    .I1(GND),
    .S(\clock16_generator/CLKFX_BUFG_INST/S_INVNOT ),
    .O(clk16_OBUF_77)
  );
  X_INV   \clock16_generator/CLKFX_BUFG_INST/SINV  (
    .I(GLOBAL_LOGIC1),
    .O(\clock16_generator/CLKFX_BUFG_INST/S_INVNOT )
  );
  X_BUFGMUX   CLK8_BUFG_INST (
    .I0(CLK8),
    .I1(GND),
    .S(\CLK8_BUFG_INST/S_INVNOT ),
    .O(clock8_OBUF_76)
  );
  X_INV   \CLK8_BUFG_INST/SINV  (
    .I(GLOBAL_LOGIC1),
    .O(\CLK8_BUFG_INST/S_INVNOT )
  );
  X_BUF   \PS2/DXMUX  (
    .I(PS1),
    .O(\PS2/DXMUX_228 )
  );
  X_BUF   \PS2/DYMUX  (
    .I(PS1_input),
    .O(\PS2/DYMUX_219 )
  );
  X_BUF   \PS2/SRINV  (
    .I(reset_IBUF_75),
    .O(\PS2/SRINV_209 )
  );
  X_BUF   \PS2/CLKINV  (
    .I(CLK8),
    .O(\PS2/CLKINV_208 )
  );
  X_BUF   \PS2/CEINV  (
    .I(clock_locked),
    .O(\PS2/CEINV_207 )
  );
  X_BUF   \PS3/DYMUX  (
    .I(PS2),
    .O(\PS3/DYMUX_245 )
  );
  X_BUF   \PS3/CLKINV  (
    .I(CLK8),
    .O(\PS3/CLKINV_242 )
  );
  X_BUF   \PS3/CEINV  (
    .I(clock_locked),
    .O(\PS3/CEINV_241 )
  );
  X_INV   \CLK8/DYMUX  (
    .I(CLK8),
    .O(\CLK8/DYMUX_262 )
  );
  X_BUF   \CLK8/CLKINV  (
    .I(clk16_OBUF_77),
    .O(\CLK8/CLKINV_259 )
  );
  X_BUF   \CLK8/CEINV  (
    .I(clock_locked),
    .O(\CLK8/CEINV_258 )
  );
  X_LUT4 #(
    .INIT ( 16'h1111 ))
  PS1_input1 (
    .ADR0(PS1),
    .ADR1(PS2),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(PS1_input)
  );
  X_FF #(
    .INIT ( 1'b0 ))
  CLOCK8_FF (
    .I(\CLK8/DYMUX_262 ),
    .CE(\CLK8/CEINV_258 ),
    .CLK(\CLK8/CLKINV_259 ),
    .SET(GND),
    .RST(\CLK8/FFY/RSTAND_268 ),
    .O(CLK8)
  );
  X_BUF   \CLK8/FFY/RSTAND  (
    .I(reset_IBUF_75),
    .O(\CLK8/FFY/RSTAND_268 )
  );
  X_FF #(
    .INIT ( 1'b0 ))
  PS1_FF (
    .I(\PS2/DYMUX_219 ),
    .CE(\PS2/CEINV_207 ),
    .CLK(\PS2/CLKINV_208 ),
    .SET(GND),
    .RST(\PS2/SRINV_209 ),
    .O(PS1)
  );
  X_FF #(
    .INIT ( 1'b0 ))
  PS2_FF (
    .I(\PS2/DXMUX_228 ),
    .CE(\PS2/CEINV_207 ),
    .CLK(\PS2/CLKINV_208 ),
    .SET(GND),
    .RST(\PS2/SRINV_209 ),
    .O(PS2)
  );
  X_FF #(
    .INIT ( 1'b0 ))
  PS3_FF (
    .I(\PS3/DYMUX_245 ),
    .CE(\PS3/CEINV_241 ),
    .CLK(\PS3/CLKINV_242 ),
    .SET(GND),
    .RST(\PS3/FFY/RSTAND_251 ),
    .O(PS3)
  );
  X_BUF   \PS3/FFY/RSTAND  (
    .I(reset_IBUF_75),
    .O(\PS3/FFY/RSTAND_251 )
  );
  X_ONE   GLOBAL_LOGIC1_VCC (
    .O(GLOBAL_LOGIC1)
  );
  X_ZERO   GLOBAL_LOGIC0_GND (
    .O(GLOBAL_LOGIC0)
  );
  X_BUF   \clock50/OUTPUT/OFF/OMUX  (
    .I(clock50_OBUF_71),
    .O(\clock50/O )
  );
  X_BUF   \clock_PS1/OUTPUT/OFF/OMUX  (
    .I(clock_PS1_OBUF_72),
    .O(\clock_PS1/O )
  );
  X_BUF   \clock_PS2/OUTPUT/OFF/OMUX  (
    .I(clock_PS2_OBUF_73),
    .O(\clock_PS2/O )
  );
  X_BUF   \clock_PS3/OUTPUT/OFF/OMUX  (
    .I(clock_PS3_OBUF_74),
    .O(\clock_PS3/O )
  );
  X_BUF   \clock8/OUTPUT/OFF/OMUX  (
    .I(clock8_OBUF_76),
    .O(\clock8/O )
  );
  X_BUF   \clk16/OUTPUT/OFF/OMUX  (
    .I(clk16_OBUF_77),
    .O(\clk16/O )
  );
  X_ZERO   NlwBlock_clock_generator_GND (
    .O(GND)
  );
  X_ONE   NlwBlock_clock_generator_VCC (
    .O(VCC)
  );
endmodule


`ifndef GLBL
`define GLBL

`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule

`endif

